ESD protecting circuit is a circuit utilized to protect an internal circuit from being damaged by an ESD voltage. FIG. 1 is a circuit diagram for a related art ESD protecting circuit 100. As shown in FIG. 1, the ESD protecting circuit 100 comprises a first ESD protecting module 101, a second ESD protecting module 103, a first voltage pad VP1, a second voltage pad VP2, and an I/O pad IP. The first voltage pad VP1 is coupled to a first predetermined voltage VDD and the second voltage pad VP2 is coupled to a second predetermined voltage VSS in a normal mode (i.e. ESD voltage does not occur). If an ESD voltage occurs, the first voltage pad VP1 or the second voltage pad VP2 is coupled to a ground, such that the current generated by the ESD voltage can flow through the first ESD protecting module 101 to the first voltage pad VP1, or flow through the second ESD protecting module 103 to the second voltage pad VP2, depending on the value of the ESD voltage. By this way, the current generated by the ESD voltage will not flow to the internal circuit such that the internal circuit can be protected. Other detail concept about the ESD protecting circuit is well known by persons skilled in the art, thus is omitted for brevity here.
However, in such structure, the swing for the signal transmitted to the internal circuit is limited to a range between the VSS and the VDD.